Nanoscale Ion Beam Lithography

Nevyan writes: "A group of researchers from the University of California, Berkeley are developing a device to carve patterns for microchips. They are using a method that creates a much smaller path with less distortion than traditional methods. They are trying to aim for a width of 50 nanometers for placing the maximum nuber of transistors. http://enews.lbl.gov/Science-Articles/Archive/mask less-chips.html"

Cool

[milgram]

Grafitti on a really small scale. Bill wuz here

Re:Cool

[bluelip]

Now I can pack more stuff onto my cheat sheets.

This could change computing economics.

[human bean]

One of the things the article passed by here was the implications of having no mask. This system cuts, carves, and dopes directly on a wafer, and is called lithography only out of courtesy.

As there is no mask, the production of each die on the wafer will be a matter of programming. That programming can be changed on the fly, allowing for individualised integrated circuits at the same relative cost as mass-produced ones. Build one or build a million, they all have almost the same cost, even if they are all slightly different.

Applications abound: serial numbered processors (of course), processors with application-enabling software embedded directly in the microcode, on-chip encryption, processors optimised for different sets of problems, the ability to mix analog and digital circuitry on the same die, the ability to order only fifty of them at a time, all this leads to increased performance and extended use.

Consider also that it may be able to test the devices on the wafer without removing them from the manufacturing equipment. This allows for far cheaper wafer-scale integration. An entire system (chipset, if you like) is carved onto a wafer, and then tested in spot. Parts that failed are then recut in different areas of the wafer, and circuitry rerouted to the new part. Results are increased yield and a much less expensive packaging scenario, not to mention the miniaturisation gain.

Particle Size?

[pythorlh]

If this is the future, and we are going to use particles to carve our silicon instead of light waves,(and yes, I know even light is particles.) When do we reach the lower limit of features that are the same size as the particles themselves?

Re:Particle Size?

[Ig0r]

If string theory is true (or as true as a unified theory can be) the smallest feature will be about a Plank length, which is the 'size' of a string, as well as point particles like photons.
I doubt that conventional electromagnetics would apply at such small sizes though.

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Re:This could change computing economics.

[Alik]

The article does claim that it's totally resist-less, but I'm not sure I buy that. AFAIK (and I'll admit that I'm not entirely a litho guru, but I did spend the summer developing lithography processes), existing maskless systems such as electron beam still need a resist, even though their mask is a software construct. I can see them maybe injecting dopants directly with an ion beam, but as I understand such things, it wouldn't be possible to create something such as a line of metal. (Working from intuition, you're not going to get a line of nonionic metal if you shoot ions at a wafer; you're going to get adulterated and possibly etched silicon.)

Your idea of altering masks on the fly to route around substrate defects is pretty cool, though. My thought is that it may end up being unprofitable to do, simply because wafers may be relatively cheap enough that the time required to test and reroute is not as cost-efficient as just chucking the chip and starting over. There's also the possibility that elements will have timing constraints which would be broken by rearranging the die. Regardless, it's still a cool idea.

Nano technology

[TeslaHz]

This is what will put all the things we like to do with computers and other electronics into wristhwatch sized devices. Upgrades are the only problem I seen with these devices.

Not all it's cracked up to be.

[Locus27]

Sure, carving things out with ions is great. We do the same kind of thing here with our FEI FIB (Fixed Ion Beam). The problem inherent is that it take *a long time*. This is not a speedy process. It's much akin to e-beam lithography, where you use a computer controlled beam of electrons to write a pattern in an energy sensitive photoresist. Again, it takes *a long time*. It can take up to 9 hours to write a repeating pattern on a 6 inch round wafer. Carving things out with an ion beam takes considerably longer. We use our FIB to carve out cross sections of a feature to attain various CD measurements or to simply look at how something plated or dep'd. It can take up to 3 hours to make a .5um x .5um x .05um cut. To pattern a whole wafer would take days.

The other problem that lies with ion beam applications is that they're even more prone to charging the wafer's surface. It's kind of like static electricity (see next paragraph), with all these ions smacking into the surface and knocking atoms away. Electrons get transferred. If the surface of the wafer is non-conductive, say... silicon dioxide, it's going to charge, and your beam is going to drift. This would be a very bad thing for ~50nm line widths. It's a very bad thing in general. Think of it as trying to spray paint something you don't have masked off in a very strong breeze. It's not going to be pretty. Like my co-workers in plating and cmp like to point out, in lithography, if we screw up, we can just strip off the resist and do it again. If you're carving out patterns with ions, you can't very well put it back.

Just a quick thing on static electricy, it's not something you want when you're trying to build semiconductors. ESD can do some pretty amazing things when you're looking on a micron or sub-micron scale. I've seen the after effects of ESD, where it melted through layers of Aluminum Oxide, Copper, and Nickle Iron. If you're building tiny transistors, ESD is something you most definitely want to stay away from. One trick we use is to dep a thin layer of gold over the wafer to distribute whatever charge builds up, but then you've got gold all over your wafer, how do you take it off? RIE or CMP it away? Sure, you could, but it's messy and time consuming.

Getting off my soapbox, ion beam "lithography" isn't in the least bit practical, and I wouldn't look for it to replace the "traditional" methods of photo and e-beam.