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Science Hardware Technology

Breakthrough May Revolutionize Microchip Patterning 62

Posted by Zonk
from the grow-your-own-chips dept.
Stony Stevenson writes "US research engineers claim to have developed a low-cost technique that allows them to create ultra-small grooves on microchips as easily as 'making a sandwich'. The simple, low-cost technique results in the self-formation of periodic lines, or gratings, separated by as little as 60nm, or less than one ten-thousandth of a millimetre. From the article: 'The new 'fracture-induced structuring' process starts when a thin polymer film is painted onto a rigid plate, such as a silicon wafer. A second plate is then placed on top, creating a polymer 'sandwich' that is heated to ensure adhesion. Finally, the two plates are prised apart. As the film fractures, it automatically breaks into two complementary sets of nanoscale gratings, one on each plate. The distance between the lines, called the period, is four times the film thickness.'"
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Breakthrough May Revolutionize Microchip Patterning

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  • Re:hmm (Score:4, Insightful)

    by cyfer2000 (548592) on Monday September 03, 2007 @12:18PM (#20452577) Journal
    The selling point of this "new" technology is "low cost". The lithography at sub 100nm is getting extreme pricey.
  • Re:hmm (Score:3, Insightful)

    by 2.7182 (819680) on Monday September 03, 2007 @12:34PM (#20452685)
    Additionally, there are so many announcements like this that you have to see it on the market to believe it.
  • by heinousjay (683506) on Monday September 03, 2007 @12:49PM (#20452805) Journal
    What are you going to wait out, exactly? Are you an executive at a chip-producing firm with the power to decide to use this?
  • Re:hmm (Score:3, Insightful)

    by MindKata (957167) on Monday September 03, 2007 @12:55PM (#20452835) Journal
    I agree the cost is high (for the FABs) but more to the point, while this is an interesting new manufacturing method, its not likely to be such a big advance, (for the chip industry) as the title to this news implies. Also I think that around about 2011, they are talking about having production 32nm fabrication. So within about 4 years from now, 32nm is going to seem very small, compared with this relatively large 60nm groves in the chip.

    Where this technology sounds potentially very useful, is in maybe applications like sensors. As its nano-scale patterns can be applied to large surface areas. That could potentially be very interesting.
  • by Alwin Henseler (640539) on Monday September 03, 2007 @01:13PM (#20453041) Homepage

    The lithography at sub 100nm is getting extreme pricey.

    Well 'pricey' is a relative term... if you're talking about the setup-cost for a factory that produces IC wafers, then yes you're talking enormous investments before the first wafers run of the production line with decent yields. But from an end-user point of view, you can buy a $50 CPU or memory module these days that may contain several hundred million transistors. Something equivalent being non-existent or 10 times more expensive a few years back...

    I'm wondering more about practical applications, and how long they will take to hit the market. For regular structures, all sorts of semiconductor memory comes to mind. Cheap flash memory? Affordable solid state drives with capacities equal or bigger than magnetic disks? For such applications production errors may not matter much. If the process is cheap, add enough redundant memory cells, decent bad cell/sector management, and the end result could be very useful.

    Anyway, looks very promising. We'll see what comes of it...

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